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Free Analog Circuit Simulation

Welcome to Spice OPUS

Basic overview

SPICE OPUS is a free general purpose circuit simulator specially suited for optimization loops. It is a recompilation of the original Berkeley source code for Windows and Linux operating systems. Later Georgia Tech Research Institute's XSpice mixed-mode simulator was added to the Berkeley code. The XSpice code model feature was enhanced so that code models can be loaded from dll/so files (.cm files).

SPICE OPUS supports Verilog-A models compiled with the OpenVAF compiler via the OSDI interface v0.3. Find out more about OpenVAF/OSDI support on our Verilog-A support page.

The simulator includes an interpreted programming language called Nutmeg, which allows interactive Spice sessions. Numerous memory leaks were fixed. The graphical part of the program was rewritten but the original syntax of the plot and iplot commands was preserved, enabling any script compatibility with other Spice compilations. We are constantly updating Spice OPUS with new semiconductor models and we are working very hard to make it as stable as possible. For more details please refer to the release history.

New: PyOPUS Release 0.10

PyOPUS is a Python library for interfacing to various simulators. It makes simulation-based design optimization simple. But it can do much more. It offers a message based parallel programming module, visualisation tools based on Matplotlib, optimization agorithms, test functions, ...
Visit the PyOPUS homepage.