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THE SLIDE RULE OF SILICON DESIGN

Free Analog Circuit Simulation

Device Models in Spice OPUS

MOS (M)

Level Model type Description
1 Mos1 MOS1, Meyer capacitance model
2 Mos2 MOS2, Meyer capacitance model
3 Mos3 MOS3, Meyer capacitance model
4 BSIM1 BSIM1 Berkeley short channel IGFET model
5 BSIM2 BSIM2 Berkeley short channel IGFET model
6 Mos6 MOS6, Meyer capacitance model
7 UFET UFET model
44 EKV EKV MOSFET model
47 BSIM3v2 BSIM3v2 Berkeley short channel IGFET model
53 BSIM3 BSIM3v3 Berkeley short channel IGFET model
54 BSIM4 BSIM4 Berkeley short channel IGFET model
55 B3SOIv1 BSIM3SOIv1 Berkeley SOI MOSFET model
56 B3SOI BSIM3SOIv2 Berkeley SOI MOSFET model
57 Soi3 STAG PD SOI MOSFET model
58 UFS UFSOI MOSFET model

JFET (J)

Level Model type Description
1 JFET JFET
2 JFET2 Parker-Skellern short channel JFET model

MESFET (Z)

Level Model type Description
1 MES MESFET model
2 HFET1 HFET model

Diode (D)

Level Model type Description
1 Diode Nongeometric junction diode model
3 Diode3 Geometric junction diode model

Other Devices

DeviceModel type
BJT (Q) BJT
Resistor (R) Resistor
Capacitor (C) Capacitor
Inductor (L) Inductor
Inductor coupling (K) mutual
Voltage controlled switch (S) Switch
Current controlled switch (W) CSwitch
Lossless transmission line (T) Tranline
Lossy transmission line (O) LTRA
Uniformly distributed RC line (U) URC
VCVS (E) VCVS
VCCS (G) VCCS
CCVS (H) CCVS
CCCS (F) CCCS
Independent voltage source (V) Vsource
Independent current source (I) Isource
Nonlinear controlled current/voltage source (B) ASRC

XSPICE code models (A)

  • Poly source - builtin code model, used for simulation of
    simulator-translated polynomial sources (POLY(N)).
  • Code models loaded from .cm library files are described in the XSPICE section of the documentation. Information about model parameters of code models are also in the .ifs files supplied with the .cm library sources. For .cm library source file location in the SPICE OPUS tree see installation instructions.