Digital nodes
A state of a digital node is determined by a logic level and a logic strength.
Available logic levels are:
- ZERO (0)
- ONE (1)
- UNKNOWN (U)
Available logic strengths are:
- STRONG (s)
- RESISTIVE (r)
- HI_IMPEDANCE (z)
- UNDETERMINED (u)
Therefore 3x4=12 digital states are available:
Strength \
Level
|
ZERO | ONE |
UNKNOWN |
STRONG |
0s |
1s |
Us |
RESISTIVE |
0r |
1r |
Ur |
HI_IMPEDANCE |
0z |
1z |
Uz |
UNDETERMINED |
0u |
1u |
Uu |
A digital state name consists of logic level and logic strength (0r = resistive zero,
1s = strong one, ...).
In case multiple digital output ports post different logic states to the same node,
the state is resolved by repeatedly applying the following table to pairs of logic
states:
State1 \
State2 |
. 0s . |
. 1s . |
. Us . |
. 0r . |
. 1r . |
. Ur . |
. 0z . |
. 1z . |
. Uz . |
. 0u . |
. 1u . |
. Uu . |
0s |
0s |
Us |
Us |
0s |
0s |
0s |
0s |
0s |
0s |
0s |
Us |
Us |
1s |
Us |
1s |
Us |
1s |
1s |
1s |
1s |
1s |
1s |
Us |
1s |
Us |
Us |
Us |
Us |
Us |
Us |
Us |
Us |
Us |
Us |
Us |
Us |
Us |
Us |
0r |
0s |
1s |
Us |
0r |
Ur |
Ur |
0r |
0r |
0r |
0u |
Uu |
Uu |
1r |
0s |
1s |
Us |
Ur |
1r |
Ur |
1r |
1r |
1r |
Uu |
1u |
Uu |
Ur |
0s |
1s |
Us |
Ur |
Ur |
Ur |
Ur |
Ur |
Ur |
Uu |
Uu |
Uu |
0z |
0s |
1s |
Us |
0r |
1r |
Ur |
0z |
Uz |
Uz |
0u |
Uu |
Uu |
1z |
0s |
1s |
Us |
0r |
1r |
Ur |
Uz |
1z |
Uz |
Uu |
1u |
Uu |
Uz |
0s |
1s |
Us |
0r |
1r |
Ur |
Uz |
Uz |
Uz |
Uu |
Uu |
Uu |
0u |
0s |
Us |
Us |
0u |
Uu |
Uu |
0u |
Uu |
Uu |
0u |
Uu |
Uu |
1u |
Us |
1s |
Us |
Uu |
1u |
Uu |
Uu |
1u |
Uu |
Uu |
1u |
Uu |
Uu |
Us |
Us |
Us |
Uu |
Uu |
Uu |
Uu |
Uu |
Uu |
Uu |
Uu |
Uu |
The rules for state conflict resolution are (the rules used to build the
previous table):
- States with stronger strengths win over states with weaker strengths.
The strongest strength is STRONG, then RESISTIVE and finally HI_IMPEDANCE.
- States with UNDETERMINED strength win out over all states except the ones
with STRONG strength.
- The UNDETERMINED strength is treated as if it was one of STRONG, RESISTIVE
or HI_IMPEDANCE where it is not known which of these three strengths is
actually applied to the logic state. The effect of this is that when
UNDETERMINED strength conflicts with STRONG, the level is the same as when
resolving the conflict between two strong states but the resulting strength
is STRONG.
- States with different levels and equal strengths produce UNKNOWN level.
- The resolution may be done pairwise in any order.
The strengths can be interpreted as:
- STRONG strength output is produced for example in a totem-pole output of a digital
gate.
- RESISTIVE strength is equivalent to the strength of the state imposed to a node by
an external pullup/pulldown resistor.
- HI_IMPEDANCE strength is equivalent to the strength of the:
- logic ONE imposed to the node by the open-collector output of a digital gate
when the transistor is closed,
- logic ZERO imposed to the node by the open-emmiter output of a digital gate
when the transistor is closed or
- output from a disabled buffer.
- UNDETERMINED strength is one of the previous three (STRONG, RESISTIVE or
HI_IMPEDANCE) where the actual strength can be any of the aforementioned three
strengths.
There is a difference between UNDETERMINED strength and UNKNOWN level.
UNKNOWN level is produced in an 'and' gate with one input set to ONE and other
to UNKNOWN. UNKNOWN level is also produced as the output from an analog-to-digital
node bridge when the input analog signal is above in_low but below in_high.
UNDETERMINED strength is produced as an output from a tristate buffer with the
'enable' input set to UNKNOWN logic level.
For a state with UNKNOWN logic level you can't tell wheather it is ZERO or ONE.
For a state with UNDETERMINED logic strength you can't tell wheather its strength
is STRONG, RESISTIVE or HI_IMPEDANCE.
Using digital nodes and code models
Let's take a look at an example:
v1 1 0 dc 0 pulse 0 1V 10ns 1ps 1ps 20ns 100ns
a1 [1] [2] atod
.model atod adc_bridge in_low=0.1 in_high=0.9 rise_delay=0.1p
+ fall_delay=0.1p
a2 2 3 inv
.model inv d_inverter rise_delay=20n fall_delay=10n input_load=10p
a3 [3] [4] dtoa
.model dtoa dac_bridge out_low=0 out_high=1 out_undef=0.5 input_load=20p
+ t_rise=20n t_fall=10n
r1 4 0 1k
This example translates analog voltage from v1 into a digital signal with the a1
node bridge instance. Then this digital signal is inverted using an inverter.
The output signal is then converted back to analog with ONE level at 2V, ZERO
level at 1V and UNKNOWN level at 1.5V. Nodes 1 and 4 are analog, nodes 2 and 3
are digital.
Analog-to-digital node bridge has 4 parameters. All voltages below in_low produce
a ZERO logic level. Voltages above in_high produce a HIGH logic level. Voltages
above in_low and below in_high produce an UNKNOWN logic level. The output from
a node bridge has STRONG strength. The rise_delay parameter determines the
propagation delay from input to output when the output changes from logic ZERO
to logic UNKNOWN or from logic UNKNOWN to logic ONE. The fall_delay is similar
except that is stands for the propagation delay when a transition from logic
ONE to logic UNKNOWN or logic UNKNOWN to logic ZERO occurs.
All digital gates have rise and fall delay parameters which are also propagation
delays for respective output logic level transitions.
A digital gate has also an input_load parameter. This parameter can be queried by
other logic gates that connect with their outputs to gate's input in order to
account for fan-in/fan-out effects of rise and fall times.

Rise and fall delays for an inverter.
The input signal is red and the output signal is green.
Rise delay is set to 20ns and fall delay to 10ns.
The signal is at the end converted from digital to analog with a digital-to-analog
node bridge. These bridges have parameters for output voltages that are produced
for all three logic levels (out_low, out_high and out_undef), an input_load
parameter with the same meaning as with other logic gates and a rise/fall time
parameters for the output voltage (t_rise, t_fall).

Rise and fall times for the digital-to-analog node bridge.
The input signal is red and the output signal is green.
Rise time is set to 20ns and fall time to 10ns.
In order to observe the state of a digital node its value must be converted from
digital to analog using a digital-to-analog node bridge and then observed as analog
voltage.
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